The present invention relates to a semiconductor integrated circuit device such as a microcontroller having a memory interface controller to which, for example, a mobile DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) is connected, and particularly to a technique effective if applied to a synchronization circuit which synchronizes read data with an internal clock.
The inventors or the like of the present application have proposed a technology wherein in a semiconductor integrated circuit such as a data processor having a memory interface controller connected with a DDR-SDRAM as described in a patent document (Japanese Unexamined Patent Publication No. 2005-78547), read data is synchronized with an internal clock on the memory interface controller side. This synchronization technique intends to determine an arriving delay of a data strobe signal relative to an internal clock, using the data strobe signal inputted in a read cycle with respect to the DDR-SDRAM as shown in FIG. 1 of the patent document 1, sample read data, based on a signal obtained by shifting the phase of the data strobe signal carried from a memory and synchronize the sampled read data with the internal clock, based on the result of determination of the arriving delay. As shown in FIG. 11 of the patent document 1, a pulse control circuit measures each signal delay at an input/output buffer and synchronizes signals DQ and DQS using it.
In the DDR-SDRAM, a clock synchronization circuit like a DLL (or PLL) is built therein, and an external clock and an internal clock are synchronized with each other. There has however been proposed a so-called mobile-spec DDR-SDRAM in which in order to attain mobile small electronic equipment typified by a cellular phone, the clock synchronization circuit like the DLL or PLL is eliminated to attain low power consumption. The inventors of the present application have discussed that a memory interface of the patent document 1 is mounted on such a microcontroller (hereinafter called simply “MCU”) as shown in FIG. 16 and the mobile DDR-SDRAM (hereinafter called simply “MB-DDR SDRAM”) is connected thereto. According to the discussions, it was revealed that the following problems arose.
In FIG. 16, a delay time td1 occurs in clocks/CK and CK with respect to the internal clock on the output side of MCU. Since the clock synchronization circuit is not mounted to MB-DDR SDRAM, a delay time td2 is generated between the input of the clocks/CK and CK and the output of signals DQ and DQS. On the input side of MCU, a delay time td3 occurs in DQin and DQSin with respect to the signals DQ and DQS. In the case of MCU, as shown in FIG. 17(A), a fluctuation width exists in delay times td1+td3 of a worst case and a best case having considered a process variation, a variation in source voltage and a change in temperature or the like. Even in the case of MB-DDR SDRAM, as shown in FIG. 17(B), a fluctuation width exists in delay times td2 of a worst case and a best case having considered a process variation, a variation in source voltage and a change in temperature or the like. As viewed from the internal clock of MCU, a large fluctuation width occurs in delay times td1+td2+td3 of a best case and a word case, obtained by adding the above (A) and (B) as shown in FIG. 17(C).
As shown in FIG. 18(A), it can be determined that when the delay times td1 through td3 are small, points at which DQSin changes from a low to high levels depending upon timing determination points t1 through t5 synchronized with an internal clock ckb exist between the determination points t1 and t2, and points at which DQSin changes from a high to low levels exist between the determination points t3 and t4. When, however, the delay times td1 through td3 become larger as shown in FIG. 18(B), a signal indefinite period of DQSin is contained in a determination region for the timing determination points t1 through t5.
This reason is as follows: In a mode for writing from MCU to MB-DDR SDRAM, MCU generates DQS and supplies it to MB-DDR SDRAM together with write data. In a mode for reading from MCU to MB-DDR SDRAM, MB-DDR SDRAM generates DQS and supplies it to MCU together with read data. Thus, since the DQS signal is bidirectionally transferred between MCU and MB-DDR SDRAM, it is placed in a floating (high impedance HiZ) state before the start of memory access.
In the read mode, the read mode is transferred from MCU to MB-DDR SDRAM. As a result, since DQS is rendered low in level by MB-DDR SDRAM, DQS is held in the floating state over a long period of time in response to an increase in each of the time delays td1 through td3. Therefore, the first determination point t1 is brought to a signal indefinite region due to the floating state in MCU. When, for example, an input circuit fetches DQSin with an indefinite level as a high level, a determination circuits makes an erroneous judgment that DQSin has already been changed to the high level at the determination point t1. Therefore, when an attempt is made to delay the determination point t1, the rise point of DQSin at the time that the delay times td1 through td3 are small as shown in FIG. 18(A), cannot be determined. Eventually, in the technology disclosed in the patent document 1, there is a limit to the speeding-up of the clock because the minimum cycle of the internal clock is determined with respect to the fluctuation width of each of the delay times td1 through td3.